A well known cause of failure for electronic integrated circuits is exposure to large and sudden electrostatic discharge. During the manufacture and use of integrated circuits, both equipment and personnel can build up substantial amounts of charge, often by triboelectric charge buildup during the contact and subsequent removal of dissimilar materials from one another. The built-up electrostatic charge can be quickly discharged when the charged item comes in contact with an integrated circuit, especially when portions of the circuit are connected to power supplies, including equipment ground. The discharge can cause significant damage to the integrated circuit by way of dielectric breakdown of oxides and other thin films, and also by high levels of conduction through relatively small areas of the circuit arising from reverse breakdown of p-n junctions on the circuit. Especially damaging results can occur if the diode enters the negative resistance region of its diode breakdown characteristics, as sufficient conduction can occur to melt conductive material such as polysilicon or aluminum, via resistive heating. The molten material can flow along the lines of the electric field to create a short circuit, such as a source-to-drain short in a MOSFET. This short circuit will remain after the electrostatic discharge has completed, and is likely to render the integrated circuit useless.
Quantification of the sensitivity of an integrated circuit to electrostatic discharge can be measured by subjecting a sample of integrated circuits to known electrostatic discharge conditions, where the amount of charge and the discharge characteristics of the charge can be controlled in a known manner. A test method is given in a standard "Test Methods and Procedures for Microelectronics", MIL-STD-883C, Method 3015.3, published by the United States Department of Defense. This method uses a "human body model" consisting of a 100 pF capacitor in series with a 1500 ohm resistor; empirical data has shown that subjecting the integrated circuit to discharge via this equivalent circuit is a good approximation for electrostatic discharge from a human being. By iteratively increasing the voltage to which the capacitor is charged prior to discharging it to a terminal of the circuit, measurement of the sensitivity threshold of a given circuit design may be made. A low failure threshold, such as 2000 volts or lower, for a circuit may require that special precautions must be taken during the handling of the circuit during its manufacture and use, adding to the production costs of both the manufacturer and the user. Of course, the number of actual electrostatic discharge failures for a particular integrated circuit will be higher for a more sensitive circuit, further adding to the costs of manufacture and use. It is clearly advantageous for both the manufacturer and the user of integrated circuits for the failure threshold to be at as high a voltage as possible.
In order to reduce the sensitivity of integrated circuits to electrostatic discharge ("ESD"), modern integrated circuits have been designed and manufactured which have protection devices at their external terminals. The intent of including such protection devices is to provide a "safe" path for the electrostatic charge to follow, such a safe path designed in such a manner that no damage occurs when electrostatic discharge occurs from a charged body to the associated terminal. These circuits have included the use of diffusion resistors and punch-through diodes. An example of such a protection device is the thick field oxide transistor described in U.S. Pat. No. 4,692,781, issued Sept. 8, 1987 and assigned to Texas Instruments Incorporated. An example of a protection device for complementary metal-oxide-semiconductor (CMOS) integrated circuits is described in copending application Ser.No. 027,103 filed Mar. 13, 1987 and assigned to Texas Instruments Incorporated.
Traditionally, output buffer circuits have not included such devices for various reasons. In integrated circuits having sufficiently large geometries, the transistors in the push-pull output buffer have been sufficiently large to safely handle fair amounts of electrostatic discharge current presented at the output terminal. The performance of the output terminal relative to electrostatic discharge protection was thus often better than the input terminals of the device. Since the electrostatic discharge protection within an integrated circuit is no better than that of its weakest terminal, little incentive existed to improve the performance of the output buffer as long as the input terminals remained weaker than the push-pull drive circuit. In addition, the attachment of protection devices to the output terminals of an integrated circuit frequently provides no protection, as the turn-on voltage of such protection devices is frequently greater than that of the output drive circuitry itself for an ESD event.
As the technology for producing integrated circuits has become more advanced, the geometries used in realizing the components within the integrated circuit have become smaller, thereby reducing the silicon cost of the circuit and increasing its operational performance. However, as the transistor sizes have become smaller, the ability of the push-pull output buffer to safely discharge electrostatic charge without damage to the circuit has reduced. In addition, the improvements to the input terminals of integrated circuits beyond the protection provided by the push-pull drive circuit has now, for some circuits, focused the emphasis of electrostatic discharge protection onto the output buffer.
In addition, some modern integrated circuits are utilizing process improvements to decrease the resistivity of diffused conductive layers. These improvements include the provision of a metal silicide layer to be formed at the top surface of diffused regions, such a layer having very low resistivity, often in conjunction with lightly-doped or graded source/drain regions. The silicide layer can be formed by the direct reaction of a sputtered or evaporated metal with the underlying diffused regions, as described in U.S. Pat. No. 4,384,301 issued on May 17, 1983 and in U.S. Pat. No. 4,545,116 issued Oct. 8, 1985, both assigned to Texas Instruments Incorporated. However, the use of lightly-doped source/drain regions and of silicide layers has been found to degrade the ESD tolerance of the circuit. Such degradation is described in "ESD Protection Reliability in 1 um CMOS Technologies", Proceedings of the IRPS (IEEE, 1986) and in "ESD Phenomena and Protection Issues in CMOS Output Buffers", Proceedings of the IRPS (IEEE, 1987). These papers discuss that the shallower diffusion depths at the channel end of the graded diffusions concentrate the conduction at the surface of the semiconductor. In addition, the silicide-clad diffusions provide a source of metal (for melt filaments) closer to the localized heating, and also likely provide, in conjunction with the graded diffusions, a greater current density-electric field product for a given magnitude of ESD stress current, further increasing the localized heating.
It is therefore an object of this invention to provide an output buffer having improved ESD tolerance.
It is a further object of this invention to provide such an output buffer which is applicable to circuits containing graded silicide-clad diffusions.
It is a further object of this invention to provide such an output buffer which may be built by existing n-channel MOS processes.
Other objects and advantages will become apparent to those of ordinary skill in the art having reference to this specification in conjunction with the drawings.